1. Field of the Invention
The present invention relates to a nonvolatile semiconductor device having electric programming/erasing function, and in particular to the nonvolatile semiconductor device, in which discrimination of data information, being written with using injection of hot electron, is made by verifying voltage of a bit line, thereby achieving a high-speed programming/erasing operation.
2. Description of Prior Art
A flush memory, having superior portability and anti-shock property, can be subjected to electric bulk erasing, therefore the needs thereof is spreading out rapidly in recent years, in particular, as a file for personal digital assistances, such as, a mobile personal computer, a digital still camera, etc. For expansion of it on the markets, it is indispensable to have high-speed operation, but with low electric power.
For the purpose of obtaining the high-speed operation, parallel operation is needed, however for realizing the high-speed operation with low electric power, there is a necessity of suppressing the current amount to be as small as possible. An operating method for achieving this is already known as a programming method of utilizing Fowler-Nordheim (FN) type tunneling phenomenon therein.
The programming operation in accordance with this method will be explained by referring to cross section views of memory cells in FIGS. 12A and 12B. A reference numeral 11 in the figures indicates a control gate, 12 a floating gate, 13 a source, 14 a drain, 15 a well, and 16 a substrate, respectively. With this method, for example, the source 13 of a memory cell selected to program is turned to OPEN, while turning the control gate to 17V and the drain 14 to 0V, as shown in the FIG. 12A, so as to inject electron into the floating gate 12 with utilizing the FN type-tunneling phenomenon, thereby performing the programming of data. In this instance, for protecting the memory cell unselected to program from the FN type-tunneling phenomenon occurring therein, unselect voltage of programming, for example, voltage of 5V is applied to the drain 14, as shown in the FIG. 12B.
With this programming method of applying such the FN type-tunneling phenomenon therein, since almost no current flows into each of the memory cells when operating in the programming mode, the high-speed programming operation can be achieved by increasing the number of cells, each of which performs the parallel operation and the programming of data as well, at the same time.
However, since the operation, so-called verification must be done, necessarily after the program operation; i.e., for conduction the verification on the data programmed, the parallel operation is also needed for that verify operation, in order to achieve the high-speed program operation. For performing this verification, there are known methods of using, such as, a current sense amplifier and a voltage sense amplifier therein.
In the method of the current sense amplifier, voltage of 0V is applied to a source line SS of the memory cell, while voltage of 1V is applied to the bit lines BLL and BLR, as shown in FIG. 13A, for example. Further, with applying the verify voltage onto the word line WL, the current Im flowing into the memory cell M and the current Iref flowing into a dummy memory cell DM at that instance are sensed to be compared with to each other in a current sense circuit 19.
On the other hand, in the method of the voltage sense amplifier, with turning the source line SS of the memory cell down to 0V, an internal supply voltage VRPCL to 3V, and a control signal to voltage; i.e., 1V+the threshold voltage of N-type MOS transistors, respectively, voltage of 1V is applied onto the bit line BLL. After that, by turning a signal RPCL to 0V and further applying the verify voltage to the word line WL, the voltage change on the bit line BLL is detected by a voltage sense circuit 21. Namely, when the threshold voltage of the memory cell M is higher than the verify voltage and no current flows therein, the voltage applied onto the bit line BLL does not change, therefore it is decided that the programming is completed, while when the threshold voltage of the memory cell M is lower than the verify voltage and current flows therein, the voltage applied onto the bit line BLL does comes down to 0V, therefore it is decided that the programming is not completed yet.
In any one of the verify methods, though current flows in the memory cell, the current is cut off by turning voltage supply from the internal supply voltage RPCL; i.e., turning the signal RPCL to 0V, in accordance with the method of the voltage sense amplifier, it is possible to operate the memory cell with the low electric power. Accordingly, it can be said that the method of the voltage sense amplifier is advantageous or profitable for obtaining the high-speed through the parallel operation.
From the mentioned above, it has been considered that using the programming method of applying such the FN type-tunneling phenomenon is the best method for realizing the high-speed operation with the low electric power, while making the verification in accordance with the method of the voltage sense amplifier.
However, by the method of programming with applying such the FN type-tunneling phenomenon, it is possible to operate the device with the low electric power, but on the contrary to this, the operation is slow in the data programming, therefore, still there is a limit to achieve the high-speed, if applying the parallel operation thereto.
Then, there is proposed a new cell, being operable with a low electric power through an improvement of programming efficiency, as well as, being fast in the programming operation, by the present inventors, as is described in Japanese Patent Application No. Hei 11-200242 (1999), filed on Jul. 14, 1999.
An outline of the programming operation in this new memory cell will be explained briefly, by referring to FIGS. 14A and 14B. A reference numeral 10 in the figures depicts a third gate; i.e., an assist gate (AG), while 11 the control gate, 12 the floating gate, 13 the source, 14 the drain, 15 the well, 16 the substrate, respectively. This memory cell comprises the third assist gate 10, as shown in the figures, in addition to the structures of the conventional memory cell having the control gate 11 and the floating gate 12.
In the programming operation, as is shown in the FIG. 14A, the programming of data is performed by injecting hot electron generated in the channel area defined between the source 13 and the drain 14m, while turning the source 13 of the selected memory cell for programming to 0V, the assist gate 10 to 2V, the control gate 11 to 12V, the drain 14 to 5V, respectively.
In this instance, for prohibiting the hot electron from generating in the unselected memory cell for programming, the drain 14 is turned to 0V as shown in the FIG. 14B. Since this memory cell has the assist gate 10, as was mentioned previously, when programming, a large electric field is formed in a lower portion of a boundary between the floating gate 12 and the assist gate 10, being wide in the horizontal direction and the vertical direction. With this, an increase is obtained in the generation of the hot electron and the injection efficiency as well; therefore it is possible to achieve the high-speed programming, in spite of the channel current, which is smaller than that in the conventional memory cell. Further, more details thereof will be explained in later, by referring to FIGS. 18 to 21.